LibreBMC stands out by replacing traditional proprietary BMC chips (like those from ASPEED) with an that runs a soft-core processor. Technology Description ISA POWER ISA Uses the open-source POWER Instruction Set Architecture . CPU Core Microwatt
: Uses the Microwatt soft-core, a tiny Open POWER ISA processor implemented in gateware.
A tiny, open-source 64-bit POWER soft-core designed for FPGAs. OpenBMC Runs the Linux Foundation's OpenBMC software stack. Hardware Spec OCP DC-SCM librebmc
: While designed for DC-SCM compatible servers, much of the development has been demonstrated on IBM AC922 systems using an interposer. 3. Key Development Tasks
| Feature | LibreBMC | OpenBMC | Aspeed AST2600 (Proprietary) | |---------|----------|---------|-------------------------------| | Hardware cost (BOM) | ~$100 | N/A (runs on $50-200 Aspeed chip) | $40-80 (volume) | | Fully open source | ✅ (HDL + firmware) | ❌ (HDL is closed, ASIC) | ❌ | | Open toolchain | ✅ (Yosys/nextpnr) | ❌ (needs vendor ARM/GCC) | ❌ | | IPMI support | ❌ (REST only) | ✅ (via phosphor-ipmi-host) | ✅ | | Production ready | ❌ | ✅ | ✅ | | Customizable peripherals | ✅ (modify Verilog) | ❌ (fixed silicon) | ❌ | | Security auditability | ✅ | 🟡 (firmware only) | ❌ | LibreBMC stands out by replacing traditional proprietary BMC
Is there a specific aspect of LibreBMC (like the FPGA implementation, the build process, or the Talos II integration) you wanted to dig deeper into?
LibreBMC represents the "final frontier" of open-source computing. The industry has successfully opened the OS (Linux), the bootloader (coreboot/U-Boot), and the instruction set (RISC-V). A tiny, open-source 64-bit POWER soft-core designed for
The most groundbreaking aspect of LibreBMC is that it doesn't just rewrite software; it targets open hardware.
: The LibreBMC SIG (Special Interest Group) holds regular meetings to discuss progress and future goals.