Symptom: Vivado freezes or takes forever to synthesize. Fix: You wrote a for-loop in Verilog that runs 10,000 times. Remember: Hardware runs in parallel. Loops are fine for testbenches, but in real RTL, loops mean you are copying the same circuit 10,000 times. Use counters instead.
Instead of re-adding files every time, type: add_files -norecurse ./src/top.v vivado student
// Sequential Logic Block always @(posedge clk) begin if (rst) begin count <= 4'b0000; // Synchronous Reset end else if (en) begin count <= count + 1; // Increment counter end end Symptom: Vivado freezes or takes forever to synthesize
A testbench ( tb_counter.v ) was created to verify the design. The testbench instantiates the counter module and applies a sequence of stimulus signals (clock toggling, reset pulses, and enable toggling). Loops are fine for testbenches, but in real
The primary objectives of this lab are:
In this laboratory exercise, a 4-bit synchronous up-counter was successfully designed in Verilog and simulated in Vivado. The behavioral simulation verified that the counter correctly implements the enable and reset functionalities. The process reinforced the importance of synchronous design principles and proficiency with the Vivado simulation workflow. No errors were encountered during synthesis or implementation.